Hardware Simulation Accelerators have become a commonly used tool in the verification of complex logic designs. For example, hardware simulation accelerators are almost a necessity in design verification of very large logic designs, especially for system level verification. These hardware simulation accelerators not only provide a design tool but also are capable of providing diagnostics to detect design errors quickly.
Typically, the more advanced hardware simulation accelerators are capable of simulating logic designs having tens or hundreds of millions of components. To provide such capacity, the hardware simulation accelerators are parallel computers employing a field of ASIC chips. A flattened netlist of the design under test is mapped to the field of chips and the segment of the netlist that is mapped to a given simulator chip is stored in a compiled format in the instruction memory (IM). For modern accelerators, the IM is located on the chip, and often takes up half or more of the die's area (chip area). As should be understood, chips contain numerous LEUs that execute the compiled design in parallel while communicating with one another.
The “netlist” describes the connectivity of a logic design. Netlists usually convey connectivity information and provide instances, nets, and perhaps some attributes. Netlists can be either physical or logical; either instance-based or net-based; and flat or hierarchical. The latter can be either folded or unfolded. An “instance” is a part of the netlist, where each instance has a “master” or “definition”. The definitions usually list the connections that can be made to a specific kind of device, and some basic properties of such device. An “instance” could be an integrated circuit chip, for example.
A “folded” hierarchy allows a single definition to be represented several times by instances. Folded hierarchies can be extremely compact. On the other hand, an “unfolded” hierarchy will not allow a definition to be used more than once in the hierarchy. Hierarchical designs can be “exploded” or “flattened” into flat designs via recursive algorithms. A “flat” design is one where only instances of primitives are allowed.
In the course of simulation, rows of the IM are read out in a sequential manner and piped to a logic evaluation unit (LEU). During the operation, a program counter advances continuously through the instruction memory one row per cycle. Sometimes, the LEUs do not need instructions during some cycles. In these cases, the program counter nevertheless advances during these cycles, and the IM contains no instructions in the rows corresponding to these cycles. This results in wasted space in the IM.
The LEU, based on received instructions, simulates the represented segment of the netlist. In hardware simulation accelerators, each LEU has a dedicated IM that supplies the instruction stream to that and only that LEU. Moreover, the IM is read at a constant speed and in a certain sequence. Also, the capacity of hardware simulation accelerators is determined largely by the size of the IM. Clearly, a need exists to reduce or optimize the amount of data stored in the IM.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.